80386and the control registersystem address register as shown in the following table .They are used to control mode ,control subsection management mechanism and page management implementation mechanism .
Control system of register CRx BIT31 BIT30—BIT12 BIT11—BIT5 BIT4BIT3BIT2BIT1BIT0CR0PG 0000000000000000ETTS EM MP PE CR1 keep CR2page faultlinear address CR3 page tablephysical page 000000000000 BIT47—BIT16 BIT15—BIT0 global descriptionsymbol table base address register GDTR interrupt descriptor table register boundaries with IDTR base address boundaries in BIT15&mdash ;BIT0 local description symbol table register LDTR select sub task state segment TR BIT31&mdash ;BIT0 BIT31—BIT0 BIT11—BIT0 base address limit property base address limit properties of < ;> ;control register from the visible ,80386four32bits in a control register,named CR0 ,CR1 ,CR2 and CR3 .
But CR1 was retainedfor future development ,the processor uses ,in 80386 cannot be used inCR1 ,otherwise it will cause an invalid instruction operation exception .CR0 includes aprocessor mode control bits shown ,including enable and disable the paging mechanism control ,Nike Outlet Online,including control of floating point coprocessor operation control .
CR2 andCR3 by using paging management mechanism .The bits in CR0 30and CR35—in the 0 to11is retained,these bits can be optional value ,must be 0 .Control register CR0 the low 16 bitsequal to 80286MSWmachine status word .
1 protection controlposition control register CR0 bitwith 0 PE markers,Dr Beats Headphones,31PGmarkers ,the two bit control segmentation and paging management mechanism of operation ,so called them protection control bit .
PE control subsection management mechanism .PE = 0 ,processor running in real mode ;PE = 1 ,processing device operating in protected mode .PG control paging management mechanism .PG = 0 ,disables paging management mechanism ,this subsection management mechanism to generate a linear address directly as a physical address using ;PG = 1 ,enable paging management mechanism ,the linear address via the paging mechanism converts a physical address .
On the paging mechanism introduced in later articles for .The following table lists the through the use of PE and PG bit selection processor mode .Because only in protected mode is enabled paging machine system ,so even though the two bits respectively 0 and 1canhave four kinds of combination ,but only three kinds of combination .
PE = 0 and PG = 1 is not a validcombination ,therefore ,using PG 1 andPE 0valuesinto the CR0 registerwill cause a general protection exception .Note that ,PG will change the system to enable or disable the paging mechanism ,thus only when the executing program code and at least a portion of the data in the linear address space and physical address space having the same address, it can change the PG bit .
PG and PE and office manager working mode of PG PE processor mode 00mode 01protected mode,disable the paging mechanism 10 illegalcombination of 11 protected mode,enable paging mechanism 2 coprocessor controlposition control in register CR0 1—4werelabeled as MP ( a ,EM arithmetic ( simulation ) a ) ,TS ( task switching position ) and ET ( extended type bit ) ,which control the operation of the floating-point coprocessor .
When the processor reset, ET bit is initialized ,indicating system digital processor type .If the system has 80387 coprocessor,then ET position 1 ;if the system in the presence of 80287 coprocessoror nonexistent assist processor ,that what ET bit 0 clear.
EM control floating point instruction execution is simulated with the software ,or by hardware implementation .When EM = 0, control of hardware floating point instruction is transmitted to the processor ;EM = 1, a floating point instruction by software simulation .
TS bits are used to speed up the task switch ,through when it is necessary coprocessor switching method for this purpose .Each when the task switching ,processor TS 1.When TS = 1,Dr Dre Headphones, the floating point instruction will generate device is not available ( DNA ) anomaly .
MP control WAIT instruction in TS = 1, whether to produce DNA anomaly .MP = 1 and TS= 1 ,WAIT produced abnormal ;MP = 0, WAIT directive ignored TS conditions ,do not generate abnormal .
3.CR2 and CR3control registerCR2 and CR3 by thepaging mechanism using the .CR2 used to occurwhen error message page exception report .When the page is abnormal, the page exception processor caused by linear address stored in the CR2 .
Operating system page exception handler can check CR2 content,thus find out the linear address space in which page caused the abnormal .CR3 is used to save thepage table of the initial physical address .
The directory is page aligned ,so only 20effective,low 12 bits are reserved for future use .To the CR3 to mount a new value, low 12 to0;but from the CR3 value,low 12 bits arethen slightly .
When using MOV command to reset the CR3 value,Moncler Jackets,will cause the paging mechanism for high speed buffer contents invalid ,with this method, can enable paging mechanism before, that the PG position before 1, a refresh page cache mechanism .
CR3 storagedevice even in the CR0 register PG bitor bits of PE 0can also be arranged in,such as in real mode can also be set to CR3 ,the initialization of the paging mechanism .In task switching ,CR3 willbe changed ,but if the new tasks of CR3 valueand the original tasks of CR3 value is the same,then the processor does not refresh the page cache ,so that when the task sharing also have faster execution speed .
80386 adds several control registers ,CR0 CR1CR2CR3CR4.CR1 register.Register the bits in CR0 0PE markers,31PGmarkers ,the two bit control segmentation and paging management mechanism of operation ,Beats By Dre Headphones,so called them protection control bit .
PE control subsection management mechanism .PE = 0 ,processor running in real mode ;PE = 1 ,the processor to run in protected mode .PG control paging management mechanism .PG = 0 ,disables paging management mechanism ,this subsection management mechanism to generate a linear address directly as a physical address using ;PG = 1 ,enable paging management mechanism ,the linear address via the paging mechanism converts a physical address .
PG and PE and office manager working mode of PG PE processor mode 00mode 01protected mode,disable the paging mechanism 10 illegalcombination of 11 protected mode,enable paging mechanism CR3 save the page directory starting physical address .
CR2 pagefor occurrence of abnormal report an error message .When the page is abnormal, the page exception processor caused by linear address stored in the CR2 .Operating system page exception handler can check CR2 content,thus find out the linear address space in which caused the abnormal page .
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